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Network processor
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#	Item
61	Software-Defined Internet Architecture: Decoupling Architecture from Infrastructure Barath Raghavan Teemu Koponen Add to Reading List Source URL: www1.icsi.berkeley.edu Language: English - Date: 2012-10-15 23:34:33 Routing Networking hardware Computer network security Forwarding plane Router Packet forwarding IP forwarding OpenFlow Network processor Network architecture Computing Internet
62	Low-latency Explicit Communication and Synchronization in Scalable Multi-core Clusters Christoforos Kachris, George Nikiforos, Vassilis Papaefstathiou, Xiaojun Yang, Stamatis Kavadias, Manolis Katevenis Institute of Comp Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2013-12-23 07:16:58 Electronic engineering Computer architecture Parallel computing Scratchpad memory CPU cache Remote direct memory access Multi-core processor Network On Chip Throughput Computing Computer memory Computer hardware
63	Exploring Parallelization for Medium Access Schemes on Many-core Software Defined Radio Architecture Xi Zhang, Junaid Ansari, Manish Arya and Petri Mähönen RWTH Aachen University, Institute for Networked Systems, Kacke Add to Reading List Source URL: conferences.sigcomm.org Language: English - Date: 2013-07-23 08:39:26 Electronics Radio resource management Computer architecture Wireless sensor network Cognitive radio Wireless networking Scheduling Multi-core processor Computer cluster Computing Concurrent computing Parallel computing
64	Gigabit Routing on a Software-exposed Tiled-microprocessor Umar Saif James W. Anderson Anthony Degangi Anant Agarwal Add to Reading List Source URL: cseweb.ucsd.edu Language: English - Date: 2005-11-28 04:51:53 Routing Networking hardware Computer networking Forwarding plane Network processor Packet switching Router Packet Processing Throughput Network architecture Computing Internet
65	On-chip Communication and Synchronization Mechanisms with Cache-Integrated Network Interfaces Stamatis Kavadias, Manolis Katevenis ∗ Michail Zampetakis, Dimitrios S. Nikolopoulos Institute of Computer Science Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2013-12-23 07:16:59 Scratchpad memory CPU cache Multi-core processor Parallel computing Remote direct memory access Stream processing Direct memory access LEON Cache Computer hardware Computing Computer memory
66	Improving Network Connection Locality on Multicore Systems Aleksey Pesterev∗ Jacob Strauss† Nickolai Zeldovich∗ Add to Reading List Source URL: pdos.csail.mit.edu Language: English - Date: 2013-02-03 21:04:37 Network socket Scheduling algorithms Parallel computing Computer networking Computer memory Transmission Control Protocol Scheduling Multi-core processor Packet Processing Computing Concurrent computing Computer hardware
67	ComView IPS ComView IPS is a compact, multi-functional device designed for remote equipment access, control, and alarm monitoring applications ComView IPS integrates a high-performance 32-bit processor, two serial ports Add to Reading List Source URL: www.csstel.com Language: English - Date: 2014-06-20 16:22:44 Internet Computer network security Network management Internet standards System administration Simple Network Management Protocol TACACS Port Network address translation Computing Network architecture Internet protocols
68	Rethinking Hardware Support for Network Analysis and Intrusion Prevention V. Paxson,1 K. Asanovi´c,2 S. Dharmapurikar,3 J. Lockwood,4 R. Pang,5 R. Sommer,1 N. Weaver1 Abstract The performance pressures on implementing e Add to Reading List Source URL: www.icir.org Language: English - Date: 2006-07-08 02:12:10 Computer security Parallel computing Network processor Intrusion prevention system Communications protocol Network switch Denial-of-service attack Transmission Control Protocol Snort Computer network security Computing Cyberwarfare
69	Shunting: A Hardware/Software Architecture for Flexible, High-Performance Network Intrusion Prevention Jose M Gonzalez Vern Paxson Add to Reading List Source URL: www.icir.org Language: English - Date: 2007-09-08 20:27:32 Transmission Control Protocol Packet Processing Intrusion prevention system Packet loss Network switch CPU cache Snort Network processor Packet capture Computer network security Computing Firewall
70	Millions of Little Minions: Using Packets for Low Latency Network Programming and Visibility Vimalkumar Jeyakumar1 , Mohammad Alizadeh2 , Yilong Geng1 , Changhoon Kim3 , David Mazières1 1 Stanford Add to Reading List Source URL: www.scs.stanford.edu Language: English - Date: 2014-08-24 01:46:17 Networking hardware Computer networking Local area networks Packet Processing Throughput Latency Transmission Control Protocol Firewall Network processor Computing Network architecture Network performance

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